integration_code/solutions/memory_models.py

"""W03: schematic address translation and a direct-mapped cache, not hardware timing."""


def translate(address, page_map, page_size=4096):
    if type(address) is not int or address<0 or type(page_size) is not int or page_size<=0:
        raise ValueError("nonnegative address and positive page size required")
    if any(type(x) is not int or x<0 for pair in page_map.items() for x in pair):
        raise ValueError("page numbers must be nonnegative integers")
    page,offset=divmod(address,page_size)
    if page not in page_map:raise KeyError("unmapped virtual page")
    return page_map[page]*page_size+offset


def direct_mapped(addresses,line_size=32,lines=2):
    if any(type(x) is not int or x<=0 for x in (line_size,lines)) or lines>65536:
        raise ValueError("bounded positive cache dimensions required")
    tags=[None]*lines
    result=[]
    for address in addresses:
        if type(address) is not int or address<0:raise ValueError("invalid address")
        block=address//line_size
        index=block%lines
        tag=block//lines
        hit=tags[index]==tag
        tags[index]=tag
        result.append({'address':address,'line':index,'tag':tag,'hit':hit})
    return result


if __name__=='__main__':
    print(translate(0x2345,{2:7}))
    print(direct_mapped([0,64,0,64]))